The present invention relates to an integrated circuit and a layout method of a chip peripheral port on used in a layout system for supporting the design of the integrated circuit, more particularly, used for realizing the input/output function of an LSI (Large-Scale Integrated circuit).
FIG. 15 is a block diagram showing a main part of a layout system for a conventional integrated circuit.
A conventional layout system 60 includes an input/output block arranging means 61 for arranging input/output blocks at the peripheral portion of a chip, a macro-block arranging means 62 for arranging functional macro-blocks (to be referred to as macro-blocks hereinafter) in the inner region of the chip, and an interwiring means 65 for performing wiring between the macro-blocks and between the macro-blocks and the input/output blocks.
In an operation of the conventional layout system 60, as shown in FIG. 16, input/output block arranging processing is performed (step S31), macro-block arranging processing is performed (step S32), and finally, wiring processing between the macro-blocks and between the macro-blocks and the input/output blocks (step S33).
As described above, in an actual chip having the above layout, as shown in FIG. 17, macro-blocks 35 are arranged in the inner region of a semiconductor chip 1 (to be referred to as a chip hereinafter), input/output blocks 36 are arranged on each side of the chip peripheral portion, and corner blocks 37 serving as the input/output blocks are arranged at the four corners of the chip. In this case, each of the input/output blocks 36, as shown in FIG. 18, includes an input/output buffer (to be referred to as a buffer hereinafter) 38 and a bonding pad (to be referred to as a pad hereinafter) 39 connected to the buffer 38, and the buffer 38 includes power supply wiring patterns 40. As shown in FIG. 19, each of the corner blocks 37 includes power supply wiring patterns 41 for connecting the power supply wiring patterns 40 of the input/output blocks 36 positioned at both the sides of the corner block 37.
As shown in FIG. 20, the pad 39 included in each of the input/output blocks 36 must be arranged at a predetermined position so as to be connected to a lead frame 43 and a bonding line 42 when a chip of an LSI is assembled, and each of the input/output blocks 36 must be arranged at a position such that the pad 39 is kept at the predetermined position. Therefore, when a chip has a large number of pads, unless the input/output blocks 36 each have a sufficiently small width are equipped, the input/output blocks cannot be arranged to satisfy the above limitation. In addition, since the corner blocks 37 are arranged at the corner portions of the chip, the normal input/output blocks 36, i.e., the pads 39, cannot be arranged. For this reason, the regions of the corner portions cannot be effectively utilized.
As described above, in each chip of an LSI laid out by a conventional layout system, especially in the peripheral portion of the chip, there are large waste regions such as intervals between input/output blocks and unused regions of the corner portions. Especially in a chip having a large number of pads, regions for positioning pads are short.